DMA Transfer

# 12 DMA Transfer

AGB has 4 DMA transfer channels.

The highest priority of these channels is DMA0, followed in order by DMA1, DMA2, and DMA3.

If a DMA with a higher priority than the currently executing DMA begins execution, the execution of the current DMA is temporarily halted, and the DMA with the higher priority is executed. Once this DMA finishes, the original DMA resumes execution from where it was halted.

Thus, the most appropriate uses of each DMA channel are those described below.

- DMA 0

Because this has the highest priority, it is not interrupted by other DMA channels. Thus, it is used for reliable processing over a limited period, as is required for purposes such as horizontal-blanking DMA.

- DMA 1 and DMA 2

These are used for direct sound functions, which require relatively high priority, or for general-purpose transfers.

- DMA 3

This is used for the most general types of transfers.

Perform the following settings when using DMA.

1. Specify the transfer source address in the source address register.

2. Specify the transfer destination address in the destination address register.

3. Set the number of data items in the word-count register.

4. Specify the transfer method to be used in the DMA control register.

[Cautions for DMA]

When transferring data to an OAM or OBJ VRAM by DMA during H-blanking, the H-blank must first be freed from the OBJ display hardware processing periods using the DISPCNT register. (See "5 Image System".)

## 12.1 DMA 0

DMA 0 allows different areas of internal memory in the main unit to access one another. It has the highest priority of the DMA channels.

### 1) Source Address

Specifies the source address using 27 bits.

The area 00000000h-07FFFFFFh (internal memory area of main unit) can be specified.

### 2) Destination Address

Specifies the destination address using 27 bits.

The area 00000000h-07FFFFFFh (internal memory area of main unit) can be specified.

### 3) Word Count

Specifies the number of bytes transferred by DMA0, using 14 bits. The number can be specified in the range 0000h-3FFFh. (When 0000h is set, 4000h bytes are transferred.)

Thus, in 16-bit data transfer mode, up to 4000h x 2=8000h bytes can be transferred, and in 32-bit data transfer mode, up to 4000h x 4=10000h bytes can be transferred.

### 4) DMA Control

DM0CNT_H [d15] DMA Enable Flag

A setting of 0 disables DMA.

A setting of 1 enables DMA, and after the transfer is completed the source an ddestination registers are restored to their last values.

[Note] Delay of 2 waits will occur before DMA is activated after this flag is set. Accessing DMA related registers during this time may cause a DMA malfunction. Do another process or insert a dummy load command instead.

DM0CNT_H [d14] Interrupt Request Enable Flag

Enables an interrupt request to be generated when DMA transfer of the specified word count has been completed.

No request is generated with a setting of 0; a request is generated with a setting of 1.

DM0CNT_H [d13-12] DMA Transfer Timing

The timing of the DMA transfer can selected from the following options.

Setting | DMA Startup Timing
00 | Start immediately
01 | Start during a V-blanking interval Starts at the beginning of a V-blanking interval (approximately 4.993 ms).
10 | Start during a H-blanking interval Starts at the beginning of a H-blanking interval (approximately 16.212 s). If this accompanies OAM access, the H-blanking interval must first be freed of OBJ display hardware processing periods. (See "5 Image System".)
11 | Prohibited Code

DM0CNT_H [d10] DMA Transfer Type

Sets the bit length of the transfer data.

With a setting of 0, the data are transferred by DMA in 16-bit (half-word) units. With a setting of 1, the data are transferred by DMA in 32-bit (word) units.

DM0CNT_H [d09] DMA Repeat

With the DMA repeat function set to ON, if V-blanking or H-blanking intervals are selected as the timing of DMA startup, DMA is restarted when the next startup condition occurs (a V-blank or H-blank). In this mode, restarting will continue as long as the DMA enable flag is not set to 0.

When the DMA repeat function is set to OFF, DMA halts as soon as the amount of data specified by the value in the word-count register has been transferred.

DM0CNT_H [d08] Source Address Control Flag

Control of the source address is specified after each DMA transfer.

A setting of 00 causes an increment.

A setting of 01 causes a decrement.

A setting of 10 causes it to be fixed.

11 is a prohibited code.

DM0CNT_H [d07] Destination Address Control Flag

Control of the destination address is specified after each DMA transfer.

A setting of 00 causes an increment.

A setting of 01 causes a decrement.

A setting of 10 causes it to be fixed.

A setting of 11 causes an increment and after all transfers end, a reload (the setting is returned to what it was when the transfer started) is done.

## 12.2 DMA 1 and 2

DMA channels 1 and 2 provide access between the Game Pak bus/internal memory of the main unit and internal memory of the main unit, or between the Game Pak bus/internal memory of the main unit and the direct sound FIFO. Transfers to direct-sound FIFO can be accomplished only by using DMA 1 and 2.

### 1) Source Address

Specifies the source address using 28 bits.

The area 00000000h-0FFFFFFFh can be specified.

### 2) Destination Address

Specifies the destination address using 27 bits.

The area 00000000h-07FFFFFFh (internal memory area of main unit) can be specified.

### 3) Word Count

Specifies the number of bytes transferred by DMA 1 and DMA 2, using 14 bits. The number can be specified in the range 0001h-3FFFh~0000h (when 0000h is set, 4000h bytes are transferred).

Thus, in 16-bit data transfer mode, up to 4000h x 2 = 8000h bytes can be transferred, and in 32-bit data transfer mode, up to 4000h x 4 = 10000h bytes can be transferred.

The word-count register setting is disabled in direct-sound FIFO transfer mode. With each request received from sound FIFO, 32 bits x 4 words of sound data are transferred.

### 4) DMA Control

DM(1,2)CNT_H [d15] DMA Enable Flag

A setting of 0 disables the DMA function.

A setting of 1 enables the DMA function, and after the transfer is completed the source and destination registers are restored to their last values.

[Note] Delay of 2 waits will occur before DMA is activated after this flag is set. Accessing DMA related registers during this time may cause a DMA malfunction. Do another process or insert a dummy load command instead.

DM(1,2)CNT_H [d14] Interrupt Request Enable Flag

Enables an interrupt request to be generated when DMA transfer of the specified word count has been completed.

No request is generated with a setting of 0; a request is generated with a setting of 1.

DM(1,2)CNT_H [d13-12] DMA Transfer Timing

The timing of the DMA transfer can be selected from the following options.

Setting | DMA Startup Timing
00 | Start Immediately
01 | Start During a V-blanking interval Starts at the beginning of a V-blanking interval (approximately 4.993 ms).
10 | Start During a H-blanking interval Starts at the beginning of a H-blanking interval (approximately 16.212 s). If this accompanies OAM access, the H-blanking interval must first be freed of OBJ display hardware processing periods. (See "Chapter 5, Image System".)
11 | Start When Request Generated by Direct-Sound FIFO Starts when a request is received form direct-sound FIFO. Specify sound FIFO as the destination address. Also, set the DMA repeat function [d09] to ON.

DM(1,2)CNT_H [d10] DMA Transfer Type

Sets the bit length of the transfer data.

With a setting of 0, the data are transferred by DMA in 16-bit (half-word) units. With a setting of 1, the data are transferred by DMA in 32-bit (word) units.

In direct-sound FIFO transfer mode, the data are transferred in 32-bit units.

DM(1,2)CNT_H [d09] DMA Repeat

With the DMA repeat function set to ON, if V-blanking or H-blanking intervals are selected as the timing of DMA startup, DMA is restarted when the next startup condition occurs (a V-blank or H-blank). In this mode, restarting will continue as long as the DMA enable flag is not set to 0.

When the DMA repeat function is set to OFF, DMA halts as soon as the amount of data specified by the value in the word-count register has been transferred.

Set this bit to 1 in direct-sound FIFO transfer mode.

DM(1,2)CNT_H [d08] Source Address Control Flag

Control of the source address is specified after each DMA transfer.

A setting of 00 causes an increment.

A setting of 01 causes a decrement.

A setting of 10 causes it to be fixed.

11 is a prohibited code.

When the Game Pak Bus has been set to the source address, make sure you select increment.

DM(1,2)CNT_H [d07] Destination Address Control Flag

Control of the destination address is specified after each DMA transfer.

A setting of 00 causes an increment.

A setting of 01 causes a decrement.

A setting of 10 causes it to be fixed.

A setting of 11 causes an increment to be carried out and then a reload(returned to setting at start of transfer) is done after every transfer is completed.

However, when in direct sound FIFO transfer mode, the destination address is fixed and unrelated to the setting.

## 12.3 DMA 3

DMA 3 provides memory access between the Game Pak bus and internal memory of the main unit, or between different areas of internal memory of the main unit.

### 1) Source Address

Specifies the source address using 28 bits.

The area 00000000h-0FFFFFFFh (internal memory of main unit and Game Pak memory area) can be specified.

### 2) Destination Address

Specifies the destination address using 28 bits.

The area 00000000h-0FFFFFFFh (internal memory area of main unit and Game Pak memory area) can be specified.

### 3) Word Count

Specifies the number of bytes transferred by DMA 3, using 16 bits. The number can be specified in the range 0001h~FFFFh~0000h (when 0000h is set, 10000h bytes are transferred).

Thus, in 16-bit data transfer mode, up to 10000 × 2 = 20000h bytes can be transferred, and in 32-bit data transfer mode, up to 10000h × 4 = 40000h bytes can be transferred.

### 4) DMA Control

DM3CNT_H [d15] DMA Enable Flag

A setting of 0 disables DMA.

A setting of 1 enables DMA, and after the transfer is completed the source and destination registers are restored to their last values.

[Note] Delay of 2 waits will occur before DMA is activated after this flag is set. Accessing DMA related registers during this time may cause a DMA malfunction. Do another process or insert a dummy load command instead.

DM3CNT_H [d14] Interrupt Request Enable Flag

Enables an interrupt request to be generated when DMA transfer of the specified word count has been completed.

No request is generated with a setting of 0; a request is generated with a setting of 1.

DM3CNT_H [d13-12] DMA Transfer Timing

The timing of the DMA transfer can selected from the following options.

Setting | DMA Startup Timing
00 | Start Immediately
01 | Start During a V-blanking Interval Starts at the beginning of a V-blanking interval (approximately 4.993 ms).
10 | Start During a H-blanking Interval Starts at the beginning of a H-blanking interval (approximately 16.212 s). If this accompanies OAM access, the H-blanking interval must first be freed of OBJ display hardware processing periods. (See "5 Image System".)
11 | Synchronize with display and start. Synchronize with start of H-Line rendering during a display interval and start.

DM3CNT_H [d11] Game Pak Data Request Transfer Flag

Should normally be set to 0.

When set to 1, DMA transfer is performed in response to a data request from the Game Pak.

[Note]

A Game Pak that supports this transfer mode is required in order to use it. In addition, it cannot be used at the same time as a Game Pak interrupt.

DM3CNT_H [d10] DMA Transfer Type

Sets the bit length of the transfer data.

With a setting of 0, the data are transferred by DMA in 16-bit (half-word) units. With a setting of 1, the data are transferred by DMA in 32-bit (word) units.

DM3CNT_H [d09] DMA Repeat

With the DMA repeat function set to ON, if V-blanking or H-blanking intervals are selected as the timing of DMA startup, DMA is restarted when the next startup condition occurs (a V-blank or H-blank). In this mode, restarting will continue as long as the DMA enable flag is not set to 0.

When the DMA repeat function is set to OFF, DMA halts as soon as the amount of data specified by the value in the word-count register has been transferred.

DM3CNT_H [d08] Source Address Control Flag

Control of the source address is specified after each DMA transfer.

A setting of 00 causes an increment.

A setting of 01 causes a decrement.

A setting of 10 causes it to be fixed.

11 is a prohibited code.

When the Game Pak Bus has been set to the source address, make sure you select increment.

DM3CNT_H [d07] Destination Address Control Flag

Control of the destination address is specified after each DMA transfer.

A setting of 00 causes an increment.

A setting of 01 causes a decrement.

A setting of 10 causes it to be fixed.

A setting of 11 causes an increment to be carried out and then a reload(returned to setting at start of transfer) is done after every transfer is completed.