AGB Memory

# 3 AGB Memory

## 3.1 Overall Memory Map

The following is the overall memory map of the AGB system.

## 3.2 Memory Configuration

In broad terms, the area 00000000h-07FFFFFFh is allocated as AGB internal memory, and 08000000-0EFFFFFFh is allocated as Game Pak memory.

### 3.2.1 AGB Internal Memory

1. System ROM
   The 16 KBytes from 000000000h is the system ROM. Various types of System Calls can be used.
2. CPU External Working RAM
   The 256 Kbytes from 02000000h is CPU External Working RAM. Its specifications are 2 Wait 16 bit Bus.
3. CPU Internal Working RAM
   The 32 Kbytes from 03000000h is CPU Internal Working RAM. It is used to store programs and data.
4. I/O and Registers
   This area is used for various registers.
5. Palette RAM
   The 1 Kbyte from 05000000h is palette RAM. It is used to assign palette colors.
6. VRAM
   The 96 Kbytes from 06000000h is the VRAM area. This area is for BG and OBJ data.
7. OAM
   The 1 Kbyte from 07000000h is Object Attribute Memory (OAM). It holds the objects to be displayed and their attributes.

### 3.2.2 Game Pak Memory

1. Game Pak ROM

   Three 32 MB Game Pak ROM spaces are allocated to the area beginning from 08000000h.

   The access speed of each of these spaces can be set individually. Thus, they are named Wait State 0, Wait State 1, and Wait State 2.

   This specification enables memory of varying access speeds in Game Pak ROM to be accessed optimally.

   The base addresses of the 3 spaces are 08000000h for Wait State 0, 0A000000h for Wait State 1, and 0C000000h for Wait State 2.

   In addition, the upper 1 Mbit of each space is allocated as flash memory. This area is used primarily for saving data.

2. Game Pak RAM

   The area beginning from 0E000000h is the Game Pak RAM area. Up to 512 Kbits of SRAM or Flash Memory can be stored here. However, it is an 8 bit data bus. Due to the specifications, any Game Pak device other than ROM must be accessed using Nintendo's library.

## 3.3 Game Pak Memory Wait Control

Although the 32 MB Game Pak memory space is mapped to the area from 08000000h onward, the 32 MB spaces beginning from 0A000000h and 0C000000h are images of the 32 MB space that starts at 08000000h.

These images enable memory to be used according to the access speed of the Game Pak memory (1-4 wait cycles).

WSCNT [d15] Game Pak Type Flag

> The System ROM uses this.

WSCNT [d14] Prefetch Buffer Flag

> When the Prefetch Buffer Flag is enabled and there is some free space, the Prefetch Buffer takes control of the Game Pak Bus during the time when the CPU is not using it, and reads Game Pak ROM data repeatedly. When the CPU tries to read instructions from the Game Pak and if it hits the Prefetch Buffer, the fetch is completed with no wait in respect to the CPU. If there is no hit, the fetch is done from the Game Pak ROM and there is a wait based on the set wait state.

> If the Prefetch Buffer Flag is disabled, the fetch is done from the Game Pak ROM. There is a wait based on the wait state associated with the fetch instruction to the Game Pak ROM in respect to the CPU. In the portion where the Prefetch Circuit does not operate, the consumed current is kept to a minimum.

WSCNT [d12-11] PHI Terminal Output Control

> Controls the output from the PHI terminal. This should always be set to 00 (No Output).

WSCNT [d10-08],[d07-05],[d04-02] Wait State Wait Control

> Individual wait cycles for each of the three areas (Wait States 0-2) that occur in Game Pak ROM can be set. The relation between the wait control settings and wait cycles is as follows. Use the appropriate settings for the device you are using.

Wait Control Value | Wait Cycles
1st Access | 2nd Access
Wait State 0 | Wait State 1 | Wait State 2
000 | 4 | 2 | 4 | 8
001 | 3 | 2 | 4 | 8
010 | 2 | 2 | 4 | 8
011 | 8 | 2 | 4 | 8
100 | 4 | 1 | 1 | 1
101 | 3 | 1 | 1 | 1
110 | 2 | 1 | 1 | 1
111 | 8 | 1 | 1 | 1

After executing the System ROM (when the User Program is started) the Wait Control Value is 000. In the Game Pak Mask ROM used with the actual manufactured product, the specifications are 1st Access/3 Wait, 2nd Access/1 Wait. In this case, set the Wait Control Value to 101.

WSCNT [d01-00] Game Pak RAM Wait Control

> Wait cycles for the Game Pak RAM can be set. The relation between the wait control settings and wait cycles is as follows. Use the appropriate settings for the device you are using.

Wait Control Value | Wait Cycles
00 | 4
01 | 3
10 | 2
11 | 8

### 3.3.1 Access Timing

The following timing charts illustrate Game Pak ROM access with 3 wait cycles on the first access and 1 wait cycle on the second.

1. Sequential Access

2. Random Access

### 3.3.2 Game Pak Bus

The Game Pak bus has a total of 32 terminals, which are described in the following table.

No. | Game Pak ROM Access | Game Pak RAM Access
Terminal | Use | Terminal | Use
1 | VDD (3.3V) |  | VDD (3.3V) |
2 | PHI |  | PHI |
3 | /WR | Write Flag | /WR | Write Flag
4 | /RD | Read Flag | /RD | Read Flag
5 | /CS | ROM Chip Selection | /CS |
6 | AD0 | Terminals used for both address(lower) and data | A0 | Address
7 | AD1 | A1
8 | AD2 | A2
9 | AD3 | A3
10 | AD4 | A4
11 | AD5 | A5
12 | AD6 | A6
13 | AD7 | A7
14 | AD8 | A8
15 | AD9 | A9
16 | AD10 | A10
17 | AD11 | A11
18 | AD12 | A12
19 | AD13 | A13
20 | AD14 | A14
21 | AD15 | A15
22 | A16 | Address (upper) | D0 | Data
23 | A17 | D1
24 | A18 | D2
25 | A19 | D3
26 | A20 | D4
27 | A21 | D5
28 | A22 | D6
29 | A23 | D7
30 | /CS2 |  | /CS2 | RAM Chip Selection
31 | /IREQ /DREQ | Terminal used for IREQ and DREQ | /IREQ /DREQ | Terminal used for IREQ and DREQ
32 | GND |  | GND |