Interrupt Control

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# 15 Interrupt Control

AGB can use 14 types of maskable hardware interrupts. If an interrupt request signal is received from a hardware item, the corresponding interrupt request flag is set in the IF register. Masking can be performed individually for interrupt request signals received from each hardware item by means of the interrupt request flag register IE.

## 1) Interrupt Master Enable Register

The entire interrupt can be masked.

When this flag is 0, all interrupts are disabled.

When 1, the setting for interrupt enable register IE is enabled.

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## 2) Interrupt Enable Register

With the interrupt enable register, each hardware interrupt can be individually masked.

By resetting the bit, the corresponding interrupt can be prohibited. Setting this to 1 enables the corresponding interrupt.

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## 3) Interrupt Request Register

When an interrupt request signal is generated from each hardware device, the corresponding interrupt request flag is set in the IF Register.

If a 1 is written to the bit which the interrupt request flag is set in, that interrupt request flag can be reset.

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## 15.1 System-Allocated Area in Work RAM

Controlling interrupts entails, along with clearing the IF register and setting the IE register, first writing an interrupt jump address at addresses $7FFC-$7FFF (total of 32 bits; see figure below) in the system allocated area of Work RAM. Processing is executed in 32-bit mode for the user interrupt. To return control from the interrupt routine to the user program, the instruction "BX LR" is used.

By changing each CPU Mode SP Initial-value, they can be set to an arbitrary memory map.

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## 15.2 Interrupt Operation

The user can arbitrarily define the Interrupt Processing Routine, but as a general rule, the Monitor ROM handles this processing. For further details on each register, please refer to "ARM7TDMI Data Sheet".

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### 15.2.1 Normal Interrupt

1. If an interrupt occurs, the CPU enters IRQ mode and control shifts to the Monitor ROM. In Monitor ROM, save each register (R0~R3, R12, LR_irq (former PC)) to the Interrupt Stack. The total is 6 words. Next, call the user interrupt processing set up in 03007FFCh. Commands called from the monitor directly must be in 32bit code format.

1. User interrupt processing is done (you can reference the cause of the interrupt with the IF Register). Also solve* problems with a stack, if necessary.
2. Restore the registers (total of 6 words) saved to the Interrupt Stack and return to user main processing.

*[Note]

Only the interrupt stack is used for normal interrupt processing. Therefore, there is a possibility of stack overflow in some cases. To solve this problem, you can either allocate a larger interrupt stack by moving SP_usr in advance or use user stack for both, by switching the CPU mode to the user mode in user interrupt processing. For the latter method, see the explanation of multiple interrupts that is discussed in the following paragraphs.

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### 15.2.2 Multiple Interrupts

1. If an interrupt occurs, the CPU enters IRQ mode and control shifts to the Monitor ROM. In Monitor ROM, save each register (R0~R3, R12, LR_irq (former PC)) to the Interrupt Stack. The total is 6 words. Next, call the user interrupt processing set up in 03007FFCh. Commands called from the monitor directly must be in 32bit code format.

2. User interrupt processing is done (you can reference the cause of the interrupt with the IF Register).

If multiple interrupts occur, SPSR_irq will be overwritten, so you must save before enabling IRQ.

The Stack problem is solved* (CPU mode is changed to user mode with system modeprivilege here.) and IRQ is enabled.

With user interrupt processing, user stack is used because the CPU is in system mode. When calling the subroutine, save LSR_usr as well.

When an interrupt occurs, Monitor ROM does the processing (1) again, and loads each register to the interrupt stack.

Continue processing (2).